As integrated circuit memory devices such as dynamic random access memories (DRAMs) become more highly integrated, the space available for each memory cell on the substrate is reduced. Accordingly, the space available for memory cell capacitors is also reduced making it more difficult to maintain the desired memory cell capacitance as integration densities increase. It may be particularly difficult to provide desired memory cell capacitances using conventional dielectric materials such as nitride/oxide (NO) or Ta.sub.2 O.sub.5.
There have thus been efforts to develop capacitor dielectric layers from materials having dielectric constants more than 100 times higher than that of NO. In particular, materials such as (Ba,Sr)TiO.sub.3 ("BST") and (Pb,Zr)TiO.sub.3 ("PZT") have been used to provide dielectric layers for memory cell capacitors. Dielectric layers formed from these materials can thus be used to increase the capacitance of a memory cell capacitor without increasing the surface area of the capacitor electrodes. When using BST or PZT to provide capacitor dielectric layers, however, Pt is generally used to provide the capacitor electrodes because Pt is relatively inert to the oxidation which may occur as a result of the high diffusivity of BST and PZT.
Pt electrodes, however, may be difficult to pattern because Pt does not readily react with conventional etching chemicals, and Pt is not easily etched using dry etching techniques such as reactive ion etching. In other words, it may be difficult to pattern a platinum layer using a conventional reactive ion etch because the reactivity between the halogen gas used in a reactive ion etch and platinum is relatively low. Other metals such as Ru and Ir may also be difficult to pattern because they are also relatively inert.
Sputtering techniques using relatively high ion energies have been developed to pattern electrodes from layers of an inert material such as Pt. When etching Pt layers using ion sputtering, however, redeposits may be formed on the sidewall of the etching mask, and the slope of the sidewall of the platinum electrode formed thereby may be reduced. The sputter etching of Pt layers is discussed in the reference by Won Jong Yoo et al. entitled "Control of Etch Slope During Etching of Pt in Ar/Cl.sub.2 /O.sub.2 Plasmas", Jpn. J. Appl. Phys., Vol. 35, 1996, pp. 2501-2504, Part 1, No. 4B, April 1996. This reference is hereby incorporated herein in its entirety by reference. As discussed in this reference, the sidewall redeposits may remain even after ashing the photoresist mask off.
As further discussed in, the Yoo et al. reference, an etchant gas including a mixture of Ar and Cl.sub.2 with more than 50% Cl.sub.2 can be reused to reduce the sidewall redeposits. While the sidewall redeposits may be reduced, however, the mask may be damaged by the Cl.sub.2 gas. Accordingly, the slope of the sidewall of the etched platinum layer may be reduced.
Notwithstanding the methods discussed above, there continues to exist a need in the art for improved methods for patterning microelectronic layers.